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 M52042FP
NTSC Video Chroma Signal Processor
REJ03F0180-0200 Rev.2.00 Sep 14, 2006
Description
The M52042FP is a semiconductor integrated circuit (IC) for picture signal processing that has been developed for NTSC system LCD color TV. This IC has a built-in luminance signal processing circuit and color signal processing circuit, which is employed to convert a composite video signal to an RGB signal.
Features
* * * * * * * * Low voltage and low power dissipation design Built-in Y/C separation circuit and external chroma trap switchable (fc is nearly equal to 1.5 MHz.) Built-in sync separation circuit Provided with Y-signal blanking function by HD pulse R.G.B. signal output Tint, contrast, picture quality and color control linearly adjustable 24-pin, shrink pitch, flat package employed Same package as in PAL system video chroma IC M52045FP, pin perfectly compatible
Application
LCD color TV and LCD color view finder
Recommended Operating Condition
Supply voltage range: 3.7 to 4.5 V Rated supply voltage: 4.0 V
Rev.2.00 Sep 14, 2006 page 1 of 13
M52042FP
Block Diagram
VCC +4 V 24 VCXO VCXO VCXO OUT MONITOR IN 23 22 21 TINT KILLER COLOR CONT. FILTER 20 19 18 APC FILTER 17 S.W. 16 KILLER OUT 15 PIX CONT. GND 14 13
VCXO
PHASE SHIFTER
TINT PIX CONT. APC DET KILLER DET
0 dB
SW
COLOR CONT.
Y LPF
0 dB
CHROMA BPF
HD BLK ACC AMP
Y AMP
R-Y DET
B-Y DET
ACC DET
PED CLAMP CP GEN
CONTRAST
R Mtx
G Mtx
B Mtx
SYNC SEP
1 VIDEO IN
2 SYNC SEP IN
3 ACC FILTER
4 SYNC OUT
5 HD IN
6
7
8
9
10
11
12 B OUT
PED CHROMA CLAMP TRAP C
Y CONTRAST R OUT G OUT OUT CONT.
Pin Arrangement
M52042FP Video input 1 SYNC separation input 2 ACC FILTER 3 SYNC separation output 4 HD pulse input 5 Pedestal-clamped capacitance 6 CHROMA TRAP 7 Y output 8 Contrast control 9 R output 10 G output 11 B output 12 (Top view) Outline: PRSP0024GA-A (24P2Q-A)
24 23 22 21 20 19 18 17 16 15 14 13
VCC (+4 V) VCXO output VCXO MONITOR VCXO input Color control Tint control KILLER FILTER APC FILTER S.W. Killer output PIX CONT. GND
Rev.2.00 Sep 14, 2006 page 2 of 13
M52042FP
Pin Description
Pin No. 1 VIDEO IN (Video input) Name Peripheral Circuit of Pins
1 VCC
Bias GND
2
SYNC SEP IN (SYNC separation input)
2
VCC
Bias GND
3
ACC FILTER
47 k
GND
3
VCC
4
SYNC OUT (SYNC separation output)
4 100 k GND 10 k
5
HD IN (HD pulse input)
5 VCC 100 k 50 k
100 k GND
Rev.2.00 Sep 14, 2006 page 3 of 13
M52042FP
Pin No. 6 Name PED CLAMP C (Pedestal-clamped capacitance) Peripheral Circuit of Pins
6 VCC
9 k2
Bias 5k GND
7
CHROMA TRAP
7 VCC
1k
GND
8
Y OUT (Y output)
VCC 150 k 40 k
8 10 k 150 k GND
9
CONTRAST CONT. (Contrast control)
VCC 5k 5k 9 36 k
30 k GND
10
R OUT (R output)
VCC 20 k 20 k
11
G OUT (G output)
Bias 360
10
( 11 ) ( 12 )
12
B OUT (B output)
GND
13 24
GND (Grounding) VCC +4 V (Power supply)
-- --
Rev.2.00 Sep 14, 2006 page 4 of 13
M52042FP
Pin No. 16 Name S.W. (Selector switch) Peripheral Circuit of Pins
16
VCC 175 k 10 k 10 k
15 k
53 k
GND
22
VCXO MONITOR
VCC
15 k 15 k
22
10 k
2k
2k
2k
2k
GND
14
PIX CONT. (Picture quality control)
VCC
14
100 k
100 k 36 k 36 k
15
KILLER OUT (Killer output)
VCC 100 k
15
100 k
150 k
17
APC FILTER
VCC
10 k
17
GND
Rev.2.00 Sep 14, 2006 page 5 of 13
M52042FP
Pin No. 18 Name KILLER FILTER Peripheral Circuit of Pins
41 k
18
GND
VCC
19
TINT CONT. (Tint control)
15 k 15 k
2 k4
160 k Bias
19
GND
20
COLOR (Color control)
VCC
20
GND
21
VCXO IN (VCXO input)
21
VCC 30 k 22 k
2k
Bias 2k GND
23
VCXO OUT (VCXO output)
VCC 500
1k 15 k
23
Bias 180 GND
Rev.2.00 Sep 14, 2006 page 6 of 13
M52042FP
Absolute Maximum Ratings
Item Supply voltage Power dissipation Operating temperature Storage temperature Thermal derating Electrostatic capacity Note: Charging capacity: 200 pF VCC Pd Topr Tstg K Vmax Symbol Ratings 4.8 680 -10 to 70 -45 to 120 5.4 200* Unit V mW C C mW/C V
Thermal Derating (Maximum Rating)
0.6
0.54
Power Dissipation Pd (W)
0.5 0.4 0.3 0.2 0.1 0 0 25 50
70
75
Ambient Temperature Ta (C)
Rev.2.00 Sep 14, 2006 page 7 of 13
M52042FP
Electrical Characteristics
(Ta = 25C, unless otherwise noted)
Item Circuit current Symbol ICC Min -- 2.20 1.25 2.7 2.7 3.7 3.7 3.7 3.7 Typ 17 2.30 1.40 3.1 3.1 4.7 4.7 4.7 4.7 Max 21 2.40 1.50 3.4 3.4 5.7 5.7 6.0 6.0 s 5 s 4 Vp-p 3 Unit mA V Test No 1 2 Test Conditions Input standard color bar signal of VCC = 4 V. Measure each output signal SYNC tip voltage at pins (1), (7) when standard color bar signal of 0.7 Vp-p is input. Input only SYNC pulse of pulse width 4.7 s to pin (1). Measure the output amplitude at pin (4) when the input SYNC pulse amplitudes are 0.2 and 0.05 Vp-p. Input only SYNC pulse of pulse width 4.7s to pin (1). Measure the output amplitude at pin (4) when the input SYNC pulse amplitudes are 0.2 and 0.05 Vp-p. Input only SYNC pulse of pulse width 4.7s to pin (1). Measure the pulse width + delay time when the input SYNC pulse amplitudes are 0.2 and 0.05 Vp-p. Measure the frequency at which the sine wave output amplitude is -3 dB when the input signal (
0.2 Vp-p
SYNC SEP section SYNC tip Vsync 1 voltage Vsync 7 SYNC output amplitude Vsync H Vsync L SYNC output pulse width Tsync H Tsync L SYNC output pulse delay Dsync H Dsync L Video section YLPF frequency characteristics (Pin (7) )
YLPF (L)
1.45
1.55
--
MHz
6
YLPF (H)
-30
-24
-21
dB
) 0.2 Vp-p
is input. Also measure the output gain at input sine wave 3.58 MHz. YLPF frequency characteristics (through mode) YLPF through 5.0 7.0 10.0 MHz 7' Measure the frequency at which the sine wave output amplitude is -3 dB when the input signal ( Ymax 1.1 1.7 1.7 Vp-p 7
0.2 Vp-p
) 0.2 Vp-p
Maximum output Video amplifier gain
is input, and V16 is 4.0 VPC input. Input standard staircase wave of 0.7 Vp-p. Measure the output amplitude at pin (12) when V9 is 0 V. Input standard staircase wave of 0.7 Vp-p. Calculate the ratio between the output amplitude at pin (12) and input amplitude when V9 is 1.7 V. Input standard staircase wave of 0.7 Vp-p, and calculate the ratio of the input amplitude to the output amplitude in Test No.8 above when V9 is changed 1 V, 2.5 V and 3.5 V. Input 1.5 MHz sine wave of 0.2 Vp-p to the input. Measure each output amplitude at pin (12) when V9 is 1.7 V, and V14 is changed to 2, 4 and 0 V and calculate the ratio between the input amplitude and the output amplitude when V14 = 2 V. Input standard staircase wave of 0.7 Vp-p and calculate the ratio between the output amplitude at pin (8) and input amplitude. With input SYNC pulse at 0.2 Vp-p, measure pin (12) output pedestal offset, and calculate ratio of the offset to that when 0.7 Vp-p standard staircase is input.
GYmax
4.0
6.0
8.0
dB
8
Contrast control characteristics
Yctrast (1) Yctrast (2, 5) Yctrast (3, 5)
1.20 -7.3 -- -3.5
2.45 -5.0 -30 -2.0
4.50 -2.7 -17 -0.5
dB
9
PIX control characteristics
XPIX (4)
dB
10
XPIX (0)
10.0
12.0
14.0
dB
Y AMP gain
GYmap
9.1
11.0
12.6
dB
11
PED offset level
Vped
0.00
0.05
0.06
--
12
Rev.2.00 Sep 14, 2006 page 8 of 13
M52042FP
Electrical Characteristics (cont.)
Item Chroma section Acc control characteristics Symbol Cacc (+4) Min 0 Typ 0.7 Max 1.5 Unit dB Test No 14 Test Conditions Input burst 0.2 Vp-p + CW 4.33 MHz shall be 0 dB. Measure the output at pin (12) when the input is changed to +4 dB and -20 dB, and calculate the ratio of the measured amplitude to the output amplitude at 0 dB. Input a chroma signal of 0.2 Vp-p to the input. Reduce the amplitude and measure the amplitude ratio when the voltage at pin (15) exceeds 2.5 V. Input burst 0.2 Vp-p + CW 4.33 MHz, change V20 to 2 V, 4 V, 3 V, 1 V and 0.5 V to measure each output (100 kHz beat) amplitude at pin (12), and calculate the ratio between the measured amplitude and the output amplitude at V20 = 1 V. Input only SYNC, and after adjusting free run, input 0.2 Vp-p CW ( -- -300 -200
0.2 Vp-p 0.2 Vp-p
Cacc (-20)
-6.0
-2.0
0
Killer operation
Ckilr
-53
-49
-43
dB
15
Color control characteristics
Cast (4) Cast (3) Cast (1) Cast (0, 5)
2 1.5 -8.5 -17 +400
2.2 2.0 -6 -13 +600
4.5 4.0 -4 -10 --
dB
16
APC pull-in range
fapc
Hz
17
), then change
the frequency. Measure the frequency when VCXO oscillator is placed in a locked condition from the free-run condition. Vp-p 18 Input CW 4.33 MHz of 0.2 Vp-p to the input, and measure the output amplitude at pin (12) when V20 = 1 V. Input CW 4.33 MHz of 0.2 Vp-p to the input, measure the output amplitude at pins (10), (11) when V20 = 1 V, and calculate the ratio of the measured amplitude to the output amplitude in Test No.18 above. Measure DC voltage at pin (15) when 0 V and 4 V are applied to pin (18).
B demodulator sensitivity Demodulated output voltage ratio
DB
0.8
1.2
1.6
R (R/B)
0.46
0.52
0.60
--
19
R (G/B)
0.20
0.30
0.40
Killer output voltage H Killer output voltage L TINT control variance
Vkiller H Vkiller L T
2.5 -- 75
3.2 0.20 85
-- 0.40 100
V
21
deg
22
TINT control characteristics
Topen
-5
+5
+15
deg
23
Input a chroma signal of 0.4 Vp-p to the input, and measure the phase variance at pin (12) when 0 V and 4 V are applied to V19. Apply B monochromatic wave, (variable phase) 0.4 Vp-p and burst 0.2 Vp-p to the input. Measure the input phase in which the output at pin (12) becomes maximum with V19 open as burst phase -180 degrees. Apply B monochromatic wave (variable phase) 0.4 Vp-p and burst 0.2 Vp-p to the input. Measure the input phase in which the output at pin (12) becomes "maximum" when V19 is 0 V and 4 V as burst phase -180 degrees.
Tmin
-55
40
-25
deg
Tmax
+30
-40
+60
HD for chroma delay
Dhd
--
2.0
2.2
s
24
Apply B monochromatic wave 0.4 Vp-p and burst 0.2 Vp-p to the input. Measure the delay time from HD pulse rise to the chroma rise of pin (12) output.
Rev.2.00 Sep 14, 2006 page 9 of 13
M52042FP
Input Signal
Standard color bar PAL (Standard staircase wave has no chroma signal)
0.7 Vp-p
0.2 Vp-p 0.2 Vp-p
Burst + CW (B monochromatic wave, etc.) PAL
0.2 Vp-p
Sine wave
0.2 Vp-p
Continuous sine wave (CW) 0.2 Vp-p
SYNC pulse
4.7 s 1H Standard HD signal 5.4 s 2.35 s
Rev.2.00 Sep 14, 2006 page 10 of 13
M52042FP
Test Circuit
VCC +4 V KILLER OUT
X'tal (3.579545 MHz) VCC VCC
VCC
3.3 M
50 pF 510 (0 to 50 pF)
+ 15 k 0.1 F
3 k 470 pF 20 k 100 k 200 pF 0.01 F
20 k
Rev.2.00 Sep 14, 2006 page 11 of 13
24 23 22 21 20 19 18 17 16 15 14 13 GND S.W. KILLER PIX VCC VCXO VCXO VCXO COLOR TINT KILLER APC (+4 V) OUT MONITOR IN CONT. CONT. FILTER FILTER OUT CONT. M52042FP VCC VCC VIDEO SYNC ACC SYNC IN SEP IN FILTER OUT 3 4 1 2 HD PED CHROMA CONTIN CLAMP.C TRAP Y OUT RAST R OUT G OUT B OUT 5 6 7 8 9 10 11 12 VCC
5.6 k
+ 18 10 F 510
10 k
Sig IN 4.7 F
10000 pF
+
100 k
+
4.7 F
2SC763 R SYNC OUT HD IN G 1.0 Vp-p (Typ.) B
680
10 k
150 k
510 k
56
10 F
470 pF
Note : The evaluation of the above application circuit should be performed with great care, because APC characteristics, etc. differ considerably according to crystal characteristics and board pattern.
M52042FP
S.W. pin: "H" external TRAP "Open" internal LPF
VCC +4 V 0.4 = Vp-p amplitude
Filter pin: "H" in normal condition "L" with the killer ON
Killer output pin: "L" in normal condition "H" with the killer ON KILLER OUT VCC VCC
Application Example
(3.579545 MHz) X'tal VCC
470 pF 3 k 120 k 100 k
VCC
+ 15 k 0.1 F
Rev.2.00 Sep 14, 2006 page 12 of 13
510 (0 to 50 pF)
200 pF 0.01 F 20 k
Open
= 2.6 VDC
24
23
22
21
20
19
18
17
16
15
14
13 GND
VCC VCXO VCXO VCXO COLOR TINT KILLER APC S.W. KILLER PIX OUT CONT. (+4 V) OUT MONITOR IN CONT. CONT. FILTER FILTER
M52042FP VCC VCC
VIDEO SYNC ACC SYNC IN SEP IN FILTER OUT 3 4 1 2 +
HD PED CHROMA CONTIN CLAMP.C TRAP Y OUT RAST R OUT G OUT B OUT 5 6 7 8 9 10 11 12 VCC
5.6 k
Sig IN 18 10 F 4.7 F
510
= 0.8 VDC
= 3.3 VDC 1000 pF
+ 10 F 510 k 470 pF
100 k
680
10 k
56
150 k
2SC763 0.7 Vp-p (Typ.) SYNC OUT HD IN 3.1 V 0.7 Vp-p (Typ.) 0.7 Vp-p (Typ.) 0 V Vth = 2.0 VDC R G B 1.0 Vp-p (Typ.)
Note : The evaluation of the above application circuit should be performed with great care, because APC characteristics, etc. differ considerably according to crystal characteristics and board pattern.
M52042FP
Package Dimensions
JEITA Package Code P-SSOP24-5.3x10.1-0.80 RENESAS Code PRSP0024GA-A Previous Code 24P2Q-A MASS[Typ.] 0.2g
24
13
HE
*1
E
F
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
1 Index mark
12
c
*2
A2
A1
D
Reference Symbol
Dimension in Millimeters
*3 e y
bp
D E A2 A A1 bp c HE e y L
Detail F
Min Nom Max 10.0 10.1 10.2 5.2 5.3 5.4 1.8 2.1 0.1 0.2 0 0.3 0.35 0.45 0.18 0.2 0.25 0 8 7.5 7.8 8.1 0.65 0.8 0.95 0.10 0.4 0.6 0.8
A
Rev.2.00 Sep 14, 2006 page 13 of 13
L
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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